PIC18F45J11-I/ML【PDF 17/228 页】IC PIC MCU FLASH 32K 2V 44-QFN

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Sheet目录3862

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2010 Microchip Technology Inc.

DS70138G-page 113

dsPIC30F3014/4013

17.3

Modes of Operation

The CAN module can operate in one of several operation

modes selected by the user. These modes include:

Initialization mode

Disable mode

Normal Operation mode

Listen Only mode

Loopback mode

Error Recognition mode

Modes are requested by setting the REQOP<2:0> bits

(CiCTRL<10:8>). Entry into a mode is Acknowledged

by monitoring the OPMODE<2:0> bits (CiCTRL<7:5>).

The module does not change the mode and the

OPMODE bits until a change in mode is acceptable,

generally during bus Idle time which is defined as at

least 11 consecutive recessive bits.

17.3.1

INITIALIZATION MODE

In the Initialization mode, the module does not transmit

or receive. The error counters are cleared and the inter-

rupt flags remain unchanged. The programmer has

access to Configuration registers that are access

restricted in other modes. The module protects the user

from accidentally violating the CAN protocol through

programming errors. All registers that control the con-

figuration of the module can not be modified while the

module is on-line. The CAN module is not allowed to

enter the Configuration mode while a transmission is

taking place. The Configuration mode serves as a lock

to protect the following registers.

All Module Control registers

Baud Rate and Interrupt Configuration registers

Bus Timing registers

Identifier Acceptance Filter registers

Identifier Acceptance Mask registers

17.3.2

DISABLE MODE

In Disable mode, the module does not transmit or

receive. The module has the ability to set the WAKIF bit

due to bus activity, however, any pending interrupts

remain and the error counters retain their value.

If the REQOP<2:0> bits (CiCTRL<10:8>) = 001, the

module enters the Module Disable mode. If the module is

active, the module waits for 11 recessive bits on the CAN

bus, detects that condition as an Idle bus, and then

accepts the module disable command. When the

OPMODE<2:0>

bits

(CiCTRL<7:5>) = 001,

that

indicates whether the module successfully went into

Module Disable mode. The I/O pins revert to normal I/O

function when the module is in the Module Disable mode.

The module can be programmed to apply a low-pass

filter function to the CiRX input line while the module or

the CPU is in Sleep mode. The WAKFIL bit

(CiCFG2<14>) enables or disables the filter.

17.3.3

NORMAL OPERATION MODE

Normal

Operating

mode

selected

when

REQOP<2:0> = 000. In this mode, the module is acti-

vated and the I/O pins assume the CAN bus functions.

The

module

transmits

and

receives

CAN

bus

messages via the CxTX and CxRX pins.

17.3.4

LISTEN ONLY MODE

If the Listen Only mode is activated, the module on the

CAN bus is passive. The transmitter buffers revert to

the port I/O function. The receive pins remain inputs.

For the receiver, no error flags or Acknowledge signals

are sent. The error counters are deactivated in this

state. The Listen Only mode can be used for detecting

the baud rate on the CAN bus. To use this, it is neces-

sary that there are at least two further nodes that

communicate with each other.

17.3.5

LISTEN ALL MESSAGES MODE

The module can be set to ignore all errors and receive

any message. The Listen All Messages mode is acti-

vated by setting the REQOP<2:0> bits to ‘111’. In this

mode, the data which is in the message assembly buf-

fer until the time an error occurred, is copied in the

receive buffer and can be read via the CPU interface.

17.3.6

LOOPBACK MODE

If the Loopback mode is activated, the module

connects the internal transmit signal to the internal

receive signal at the module boundary. The transmit

and receive pins revert to their port I/O function.

Note:

Typically, if the CAN module is allowed to

transmit in a particular mode of operation

and a transmission is requested immedi-

ately after the CAN module has been

placed in that mode of operation, the mod-

ule waits for 11 consecutive recessive bits

on the bus before starting transmission. If

the user switches to Disable mode within

this 11-bit period, then this transmission is

aborted and the corresponding TXABT bit

is set and TXREQ bit is cleared.

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